1. Field of the Invention
The present invention concerns an SRAM memory cell structure by using a thin film transistor and a method of forming the SRAM memory cell structure.
2. Description of the Related Arts
Utilization of a thin film transistor, in particular, a thin film transistor having, for example, a poly-Si active layer to a liquid crystal display apparatus, static random access memory (SRAM) or the like has started and its technical importance has been increased more and more in recent years.
A poly-Si thin film transistor (hereinafter sometimes simply referred to as TFT) has an undesirable characteristic of small ON-current and large OFF current due to the effect of traps present at the grain boundary of poly-Si, for which an improvement has been desired.
In particular, in a case of applying TFT to an SRAM, it is extremely important to decrease the OFF current, that is, leak current of TFT in order to keep a data possessing current at a low level.
It has been considered for the TFT leak current that it is mainly composed of a tunnel current by way of grain boundary-traps as described, for example, The Technical Report of Electron Information Communication Society, SDM 90-141 (Kato, 1990) or the like, and an effort has been made for the creasing the grain boundary traps. For this purpose, there has been mainly adopted, for example, a method of increasing the size of grains and substantially decreasing the number of grain boundaries contained in TFT thereby decreasing the traps as well, or a method of inactivating traps by utilizing hydrogen contained in plasma SIN.
However, no satisfactory characteristic has yet been obtained even by using the above-mentioned method and a guiding principle for improving the characteristic is not definite at present.
FIG. 1 shows an example of a common CMOS-SRAM memory structure using a thin film transistor (hereinafter referred to as TFT). The figure shows a substrate structure of a unit cell in which word transistors and driver transistors are formed on an Si substrate, load devices are stacked on the upper layer thereof, a word line 7 is disposed to the center of the cell, and two driver transistors (electrodes thereof are shown by 8, 9) are disposed on both sides substantially in parallel and in a point-to-point symmetry with respect to the center of the cell.
FIG. 2 shows a cross sectional view taken along line X-X' in FIG. 1, FIG. 3 is a cross sectional view taken along line Y-Y' and FIG. 4 is a circuit diagram for the SRAM memory cell.
In FIG. 4 showing the memory cell circuit, transistors 1, 6 are word transistors, transistors 2, 5 are driver transistors and transistors 3, 4 are load transistors.
In highly integrated memories after 4MSRAM, it is customary that word transistors and driver transistors are formed on an SI substrate and load transistors are constituted with PMOS-TFT. FIG. 1 shows a structure as an example, in which only the arrangement for gate electrodes of the word transistors and the driver transistor, as well as relevant contacts are shown. That is, the electrode 7 is a word line, electrodes 8, 9 are driver transistors and a portion depicted by reference numeral 10 in FIG. 1 is an interdevice isolation region for separating them. A signal taken out of a node contact 11 passes through the word transistor 7 and is then taken out by way of a diffusion layer below the contact of the electrode 8 from a bit contact 12. In the drawing, the signal is shown at 18.
In this prior art, for transmitting the signal from the memory node contact 11 to the bit contact 12, it has to be passed through the diffusion layer below the gate electrode 8 of the driver transistor (refer to as a bypass diffusion layer 13. Also refer to FIGS. 2 and 3), which brings about problems such as increase of resistance, increase of capacitance and difficulty in ensuring the insulation withstand voltage.
FIGS. 2 and 3 are fragmentary cross sectional views for this prior art. For the doping to this portion, impurities are injected through a resist mask at a timing of threshold controlling ion implantation.